View EMLS232UA_4221856.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
Document Title
512K x 32 x 4Banks Low Power SDRAM Specificaton
Revision History
Revision No.
0.0 0.1 Initial Draft DC parameter values are changed DC parameter values are changed. Wafer spec & PAD allocation are attached. PAD coordinates are not fixed (TBD). Special MRS mode (Wrap off) supported. Pad allocation changed. (NC Pad added to right bottom) Pad coordinates are updated. Pad allocation changed. (BA0,BA1) DC parameter values are revised.
History
Draft Date
Apr 7 , 2006 Jul 21 , 2006
Remark
Draft Advanced
0.2
Sep 2 , 2006
Advanced
0.3 0.4 0.5 0.6
Sep 21 , 2006 Dec 6 , 2006 Dec 19 , 2006 Sep 10 , 2007
Advanced Advanced Advanced
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Emerging Memory & Logic Solutions Inc.
Zip Code : 690-717
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office.
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
512K x 32Bit x 4 Banks Low Power SDRAM FEATURES GENERAL DESCRIPTION
1.8V power supply. LVCMOS compatible with multiplexed address. Four banks operation. MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length(1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). EMRS cycle with address key programs. All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation. Special Function Support. . PASR(Partial Array Self Refresh). . Internal auto TCSR (Temperature Compensated Self Refresh) . DS (Driver Strength) . Deep power down DQM for masking. Auto refresh. 64 refresh period (4K cycle). Commercial Temperature Operation (-0 ~ 70 ) Extended Temperature Operation (-25 ~ 85 )

The EMLS232UA series is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 534,288 words by 32 bits, fabricated with Ramsway's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.
ORDERING INFORMATION
Part No. EMLS232UAW-6(E) Max Freq. 133 (CL3), 100 (CL2) Interface LVCMOS Package Wafer Biz.
NOTE : 1. In case of 40 Frequency, CL1 can be supported. 2. Ramsway are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in ramsway when considering the use of a product contained herein for any specific purpose, such as medical,aerospace, nuclear, military, vehicular or undersea repeater use.

Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
General Wafer Specifications
Process Technology : 0.125um Trench DRAM Process Wafer thickness : 725 +/- 25um Typical Pad Open Size : 70.2um x 70.2um Minimum Pad Pitch : 93.6um Wafer Diameter : 8-inch
| | | | |
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
PAD FUNCTION DESCRIPTION
Pad CLK CS CKE Name System clock Chip select Clock enable Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, Column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins.: DQ0 ~ 31 Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity This pin is recommended to be left No Connection on the device.
A0 ~ A10
Address
BA0 ~ BA1 RAS CAS WE DQM0~DQM3 DQ0 ~ n VDD/VSS VDDQ/VSSQ N.C/RFU
Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground
Data output power/ground
No connection /reserved for future use
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
FUNCTIONAL BLOCK DIAGRAM
LWE LDQM
I/O Control
Data Input Register Bank Select 512K x 32 Sense AMP Row Decoder Row Buffer 512K x 32 512K x 32 512K x 32
Refresh Counter
Output Buffer
DQi
Address Register
CLK ADD
LCBR
Column Decoder Col. Buffer Latency & Burst Length Programming Register
LRAS
LCKE LRAS LCBR LWE
LCAS
Timing Register
LWCBR
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM0~DQM3
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current NOTE :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Symbol VIN,VOUT VDD, VDDQ TSTG PD IOS
Value -1.0 ~ 2.6 -1.0 ~ 2.6
Unit
V
V
-55 ~ +150 1.0 50
W
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25oC~ 85oC for Extended, 0oC~ 70oC for Commercial) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current NOTE :
1. Under all conditions VDDQ must be less than or equal to VDD. 2.VIH (max) = 2.2V AC. The overshoot voltage duration is 3 3.VIL (min) = -1.0V AC. The undershoot voltage duration is 3 . 4.Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. 5.Dout is disabled, 0V VOUT VDDQ.

Symbol VDD VDDQ VIH VIL VOH VOL ILI
Min 1.7 1.7 0.8 x VDDQ -0.3 0.9 x VDDQ -2
Typ 1.8 1.8 1.8 0 -
Max 1.95 1.95 VDDQ + 0.3 0.3 0.2
Unit V V V V V V
Note 1 1 2 3
IOH = -0.1
IOL = 0.1 4
2
CAPACITANCE
Pin Clock RAS, CAS, WE, CS, CKE, DQM0~DQM3 Address DQ0 ~ DQ31
(c)
(VDD = 1.8V, TA = 23
, f=1 , VREF =0.9V
50
) Symbol CCLK CIN CADD COUT Min 1.5 1.5 1.5 2.0 Max 3.5
Unit
Note
3.0

3.0 4.5
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
DC CHARACTERISRICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0oC~ 70oC for Extended, -25oC~ 85oC for Commercial)
Parameter Symbol Test Condition Active mode; Burst length = 2; Read or Write; tRC tRC(min); CL=3; tCC=10 IO= 0
Version 133MHz
Unit
Note
1 Bank Deep Power Down mode current ICC7
130
135 10
140
150
NOTE :
1.Measured with outputs open. 2.Refresh period is 64 . 3.Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Self Refresh Current
ICC6
CKE
0.2V
4 Banks 2 Banks
210 160
220 170
230 180
250 190
Internal Auto TCSR
Max 15
Max 45
Max 70
Max 85
Refresh Current
ICC5
tARFC
tARFC(min), tCC = 10
80
Operating Current (Burst Mode)
ICC4
IO = 0 Page burst, CL=3, Read or Write, tCC = 10 4Banks Activated
75

ICC3NS
CKE VIH(min), CLK Input signals are stable
VIL(max), tCC =
10
Active Standby Current in non power-down mode (One Bank Active)
ICC3N
CKE VIH(min), CS VIH(min), tCC = 10 Input signals are changed one time during 20
ICC3PS
CKE & CLK
VIL(max), tCC =
0.5 20
Active Standby Current in power-down mode
ICC3P
CKE
VIL(max), tCC = 10
ICC2NS
CKE VIH(min), CLK Input signals are stable
VIL(max), tCC =
2 0.5
Precharge Standby Current in non power-down mode
ICC2N
CKE VIH(min), CS VIH(min), tCC = 10 Input signals are changed one time during 20
ICC2PS
CKE & CLK
VIL(max), tCC =
0.15 15
Precharge Standby Current in power-down mode
ICC2P
CKE
VIL(max), tCC=10
0.15
Operating Current (One Bank Active)
ICC1
65
1
1
2
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
AC OPERATING TEST CONDITIONS
Parameter AC input levels(Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 0.9 0.5

(VDD = 1.7V ~ 1.95V, TA = 0
~ 70
for Commercial, -25
~85
for Extendedl)
Value VDDQ / 0.2 VDDQ
Unit V V
!
tr/tf = 1/1 0.5 VDDQ
V
See Figure 2
1.8V 13.9"
Vtt=0.5 50$ Z0=50#
# # #
VDDQ
VOH (DC) =VDDQ - 0.2V, IOH = -0.1 20

10.6"
CL
Figure 1. DC Output Load Circuit
Figure 2. AC Output Load Circuit
%
Output
%
Output
VOL (DC) = 0.2V, IOL = 0.1
20% 10 5 2.5%
(Full DS) (Half DS) (Quarter DS) (Octant DS)
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Auto refresh cycle time Exit self refresh to active command Col. address to col. address delay Number of valid output data Number of valid output data Number of valid output data NOTE :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum dealy is required to complete write. 3. Maximum burst refresh cycle: 8 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop.
Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tARFC(min) tSRFX(min) tCCD(min) CAS latency=3 CAS latency=2 CAS latency=1
Value 15
Unit
!
Note 1 1
tRDL + tRP 1 1 80
!
CLK CLK
!
120 1 2 1 -
CLK
ea
!
15
!
67.5
!
70,000
!
45
!
22.5
!
22.5
1 1
1 2 2 2 3
4
5
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter CAS latency=3 CLK cycle time CAS latency=2 CAS latency=1 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=1 CAS latency=3 Output data hold time CAS latency=2 CAS latency=1 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CAS latency=3 CLK to output in Hi-Z CAS latency=2 CAS latency=1 NOTE : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1 , (tr/2-0.5) should be added to the parameter. 3. tAC(max) value is measured at the low Vdd(1.7V) and cold temperature(-25 ). tAC is measured in the device with half driver strength(CL=10pF) and under the AC output load condition. 4. Assumed input rise and fall time (tr & tf) = 1 . If tr & tf is longer than 1 , transient time compensation should be considered, i.e., [(tr + tf)/2-1] should be added to the parameter.

Symbol tCC tCC tCC tAC tAC tAC tOH tOH tOH tCH tCL tSS tSH tSLZ
Value Min 7.5 Max
Unit
Note
6
!
7 2.5
!
2.5 !
2.5
!
2.5
!
2.0
!
1
!
1 6
!
tSHZ
7 -
!
10
1000
1
1,2,3
2
4 4 4 4 2
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 H H CKEn X H L H X X CS L L L H L L RAS L L H X L H CAS L L H X H L WE L H H X H H DQM X X BA0, 1 A10/AP OP CODE X A9 ~ A0 Note 1, 2 3 3 3 3
L H H
X X X V V
X Row Address L H L H X V X L H X Column Address (A0~A7) Column Address (A0~A7)
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
4 4, 5 4 4, 5 6
H H H
X X X
L L L H L X H H L L H L
H H L X V X X X V H X V X
L H H X V X X X V H X V
L L L X V X X X V L X V
X X X
V
Clock Suspend or Active Power Down
H L H
L H L
X X X
X
X X
L
H
Entry Deep Power Down Exit DQM No Operation Command
H
L
X X X V X X 7
L H H
H
X
H L
X H
X H
X H
X
(V=Valid, X =Don'care, H=Logic High, L=Logic Low) t
NOTE :
1. OP Code : Operand Code A0 ~ A10 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. Partial self refresh can be issued only after setting partial self refresh mode of EMRS. 4. BA0 ~BA1 : Bank select addresses. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with Normal MRS Address BA0 ~ BA1 "0" Setting for Normal MRS A10/AP*1 Wrap Mode 0: Wrap on 1: Wrap off A9*3 W.B.L A8 A7 A6 A5 A4 A3 A2 A1 A0
Function
Test Mode
CAS Latency
BT
Burst Length
Normal MRS Mode
Test Mode A8 0 0 1 1 A7 0 1 0 1 Type
Mode Register Set Reserved Reserved Reserved
CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency
Reserved
Burst Type A3 0 1 Type Sequential Interleave Mode Select BA1 BA0 Mode A2 0 0 0 0 1 0 0 setting for Normal MRS 1 1 1 A1 0 0 1 1 0 0 1 1
Burst Length A0 0 1 0 1 0 1 0 1 BT=0 1 2 4 8
Reserved Reserved Reserved Full Page
BT=1 1 2 4 8
Reserved Reserved Reserved Reserved
1 2 3
Reserved Reserved Reserved Reserved
Write Burst Length A9 0 1 Length
Burst Single Bit
Full Page Length x32 : 64Mb(256)
Register Programmed with Extended MRS Address Function BA1 BA0 A10/AP A9 RFU*2 A8 A7 A6 DS A5 A4 A3 A2 A1 PASR A0
Mode Select
RFU*2
EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength)
Mode Select BA1 0 0 1 1 BA0 0 1 0 1 MODE Normal MRS Reserved EMRS for Low Power SDRAM Reserved Reserved Address A10/AP 0 A9 0 A8 0 A7 0 A4 0 A3 0 A6 0 0 1 1 Driver Strength A5 0 1 0 1 Driver Strength Full 1/2 (default) 1/4 1/8 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 PASR Size of Refreshed Array Full Banks (default) Two Banks (Bank 0,1) One Bank (Bank 0) Reserved Reserved Reserved Reserved Reserved
NOTE :
1. If A10/AP is high during MRS cycle, "Wrap off mode" function will be enabled. This mode support only sequential burst type. 2. RFU(Reserved for future use) should stay "0" during MRS cycle. 3. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
Partial Array Self Refresh
1. In order to save power consumption, Low Power SDRAM has PASR option. 2. Low Power SDRAM supports 3 kinds of PASR in self refresh mode : Four banks, Two banks and One bank.
BA1=0 BA1=0 BA0=0 BA0=1
BA1=0 BA1=0 BA0=0 BA0=1
BA1=0 BA1=0 BA0=0 BA0=1 BA1=1 BA1=1 BA0=0 BA0=1
- One Bank (Bank0)
BA1=1 BA1=1 BA0=0 BA0=1
- Four Banks
BA1=1 BA1=1 BA0=0 BA0=1
- Two Banks (Bank0,1)
Partial Self Refresh Area
Internal Temperature Compensated Self Refresh (TCSR)
NOTE :
1. In order to save power consumption,Low power SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the two temperature range : Max 85 , Max 70 , Max 45 , Max 15 2. If the EMRS for exteranl TCSR is issued by the controller, this EMRS code for TCRS is ignored. 3. It has +/- 5 tolerance.

Temperature Range Max 85
Max 70
Max. 45 Max 15
3
220 210
170 160
135 130
B. POWER UP SEQUENCE
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. -Apply VDD before or at the same time as VDDQ. 2. Maintain stable power, stable clock and NOP input condition for a mininmun of 200& . 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. 6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS. EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used. The default state without EMRS command issued is half driver strength and full array refreshed. The device is now ready for the operation selected by EMRS. For operating with DS or PASR, set DS or PASR mode in EMRS setting stage. In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.

Self Refresh Current (Icc6) Full Array 250 230 1/2 of Full Array 190 180 1/4 of Full Array 150 140
Unit
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
C. BURST SEQUENCE (Wrap on mode) 1. BURST LENGTH = 4
Initial Address A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 1 2 3 0 Sequential 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2 Interleave 2 3 0 1 3 2 1 0
2. BURST LENGTH = 8
Initial Address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 Sequential 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 Interleave 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
Rev 0.6

▲Up To Search▲

Price & Availability of EMLS232UA

	To Download EMLS232UA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .